LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY df IS
	PORT(
		clk,d:IN STD_LOGIC;
		q:OUT STD_LOGIC);
END df;
ARCHITECTURE dff OF df IS
BEGIN
  PROCESS(clk)
	BEGIN
	 IF (clk'EVENT and clk='1') THEN 
         q<=d;
	 END IF;
  END PROCESS;
END dff;